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a sah i k a se i e m d c o rpora tion ms0932 - e - 01 jan - 09 1 programm a ble c lock g e ne r ator ak81 42 features suppl y voltage: 3.0 ? 3.6 v( m ain) 1.8 ? 3.3 v(interf a ce) low current consumption: 5.0m a (t y p.) cry stal unit osc illation: 16.0m hz ? 32.0m hz input frequenc y: 2.0m hz ? 67.0m hz output frequen c y: 4.0m hz ? 200m hz low jitter perform ance: 15 ps (t y p.) pe riod 1 s operating t emperature r ange: - 3 0 to +85 i2c interf ace: pac kage: 16 - pin t ssop description t he ak8 142 is a programm able clock generat or ic with an int egrate d fraction al n pl l. h igh ly accurate clock s can be o utp ut f rom an externa l m aster clock or a cr y st al un it. applications general pu r pose cloc k g enerator block diagr am a k8 14 2 regi ster prog ra mmable clo ck gen erator c r y st a l osc vdd x out x in e x t in ckout fsel sda scl reset a0 a1 gnd 1 c o nt r ol r e g i st e r0 refout pha se comparator charge p u mp lpf nd iv S modu l ator o d iv md iv fr a c[17:0] int [ 6 :0] ckou t en [1:0] out c[2 :0] odi v pg [ 3 :0] m di v pg [ 2 :0] m di vc [ 3 :0] ckoff [0] ckoff [ 1 ] refou t en [1:0] http://
a k8 1 42 jan- 09 ms093 2 - e - 01 - 2 - t he brand name of a kemd ? s ic ? s pin description pac kage: 16 - pin t sso p ( t op view) pin n o. pin name pin t y pe description 1 x in in crystal connection. please input e x ternal clock to x in w hen the ex ternal clock is used. 2 reset in reset signal input pin. high pulse reset t he regis t er and digi t al part o f pll . hi: reset lo: n ormal opera t io n 3 fsel in frequency setting register bank selection pin . hi: register bank1 lo: register bank0 valid w hen ctlfsel= ? 1 ? of r egister f7 . 4 vdd1 -- 3.3v po w er supply for pll co r e. 5 gnd 1 -- ground 1. 6 gnd 2 -- ground 2 . 7 vdd2 -- po w er supply fo r clock outpu t buffer. 1.8v or 3.3v can be used. 8 ck o ut out clock ou t put. 9 refout out pll r eference c lock output. 10 s cl in serial in t erface c lock input. 11 sda in / out serial data input and output pin. open drain. 12 vdd3 -- po w er supply for se r ial int erface. 1.8v or 3.3v can be used. 13 gnd3 -- ground 3 . 14 a1 in device address set t ing pin. 15 a0 in device address set t ing pin. 16 x out in crystal connection . please keep this pin open if t he ex ternal clock is input t o x i n pin. ordering information part number marking shipping p ackaging package temperat ure range AK8142 8142 tape and reel 16 - pin tssop - 3 0 to 85 16:xout 15:a0 14:a1 13:gnd3 12:vdd3 11:sda 10:scl 9:refout 1:xin 2:reset 3:fset 4:vd d1 5:gnd1 6:gnd2 7:vd d2 8:ckout
a k8 1 42 ms0932 - e - 01 jan- 09 - 3 - t he brand name of a kemd ? s ic ? s a b solute maximum rating over op erat ing f ree - a ir tem perature rang e un less ot he rw ise not ed (1) items s y mbol ratings unit s upply v oltage vdd - 0.3 to 4.6 v input v oltage vin vss - 0.3 to vdd+0.3 v input c urrent ( any pins e x cept supplies) i in 10 ma st orage t emperature tstg - 55 to 130 c note (1) stress beyond t hose lis t ed under ? a bsolu t e m a x imum ra t ings ? may cause permanent damage to the device. these are st r ess ra t ings only. f unc t ional operation of the device a t these or any other conditions beyond t hose indicated under ? r ecommended ope r ating conditions ? is not implied. e x posure t o absolute - ma x imum - rating conditions for e x tended pe r iods may affect device reliability. electrical pa r amete r s a r e guaran t eed only o v er the r ecommended opera t ing tempera t ure r ange. t his devic e is m anu f actured on a cm o s process, t he r e f ore, ge n erical l y suscepti b le t o da m age b y excessive s t ati c v o lt a ge. f a ilure t o obse r v e proper ha n dling an d ins t allati o n procedures ca n cause d a m age . akemd reco m m ends that t his d evice is ha n dle d w it h a ppropr iate precautions. recommended oper ation condition s parameter s y mbol conditions m in t yp m ax unit operating t empe r ature ta - 3 0 85 c vdd1 3.0 3.3 3.6 v supply voltage vdd2 vdd3 1.7 1.8 vdd1 v input c lock frequency1 fin1 qua rtz oscillator input 16.0 24.0 32.0 mhz input c lock frequency2 fin2 e x ternal inpu t , > 0 .8 vpp 2.0 67.0 mhz input c lock duty cycle e x ternal input 30 50 70 % cp1 pin: ckout 4 m h z ? 100 m hz 100 m hz ? 150 m hz 150 m hz ? 200 m hz 15 10 8 p f output load capacitance cp2 pin: refout 2 m h z ? 67.0 m hz 25 pf esd sensiti v e d ev ice
a k8 1 42 jan- 09 ms093 2 - e - 01 - 4 - t he brand name of a kemd ? s ic ? s dc characteristics all specificat ions at vdd1: 3.3v, vdd2/vdd3: 1.8 v , ta: - 3 0 to +85 , unless otherw ise not ed parameter s y mbol conditions min t yp max unit high level input voltage 1 v ih 1 0. 7 vdd 1 v lo w level input vol t age 1 v il 1 pin: a0, a1 , fsel, reset 0.3vdd 1 v high level input voltage 2 (1) v ih 2 0. 7 vdd 3 v lo w level input vol t age 2 (1) v il 2 pin: scl, sda 0.3vdd 3 v input current i l pin: a0, a1 , fsel , reset - 10 +10 a high level outpu t voltage 1 v oh 1 refout, clkout ioh= - 4ma 0.8vdd 2 v lo w level ou t put vol t age 1 v ol 1 refout, clkout iol = +4ma 0.2vdd 2 v lo w level ou t put volt age 2 v ol 2 pin: sda iol = + 3 ma , open drain 0.4 v i dd 1 no load , vdd1 3.5 ma i dd 2 no load, vdd2 0.95 ma c urrent c onsump t ion (2), (3) i dd 3 no load, vdd3 0.05 ma po w er do w n current i pd oe= ? l ? fsel= ? l ? or open 0 10 a (1) do not e x ceed the voltage vdd3. (2) e x ternal clock mode.(s c l=h, sda=h), no load. (3) x in = 16m h z, cko u t = 24.5759989 m h z. regist er: ff=03hex , fe=74hex , fd=bche x , fc=25hex , fb=32hex , fa=61hex
a k8 1 42 ms0932 - e - 01 jan- 09 - 5 - t he brand name of a kemd ? s ic ? s a c characteristics all specificat ions at vdd1: 3.3v, vd d2/vdd3: 1.8v , ta: - 3 0 to +85 , unless otherw ise not ed (1) phase comparison frequency = input frequency / m div value. refer to register address fa. (2) vco frequency = phase comparison fr equency x ndiv value. refer to r egister addr ess fc. (3) refer to r egister addr ess fb. (4) w it h t he load capacitance specified by the recommended operation conditions. (5) q uartz oscillator input or ex ternal clock input w ith 50% duty. (6) the time that output reaches t he tar get fr equency w ithin accuracy of 0.1% from the point t hat the fsel is sw itched. (7) design value parameter s y mbol conditions min typ m ax unit phase comparison p eriod (1) 2 4 mhz vco frequency (2) cko u t 100 mhz cko u t, divided 4.0 100 mhz output clock frequency (3) cko u t, not divided 100 200 mhz refout (5) 40 50 60 cko u t, divided 45 50 55 output c lock d uty cycle (4)(7) cko u t, not divided 30 50 70 % refout, 0.2vdd to 0.8vdd 2 m h z ? 66.0 m hz 3.0 ns cko u t, 0.2vdd to 0 . 8vdd 4 m h z ? 100 m hz 3.0 ns cko u t, 0.2vdd to 0 . 8vdd 100 m hz ? 150 m hz 2.5 ns output c lock r ise t ime (4)(7) t r i se cko u t, 0.2vdd to 0 . 8vdd 150 m hz ? 200 m hz 2.0 ns refout, 0.2vdd to 0.8vdd 2 m h z ? 66.0 m hz 3.0 ns cko u t, 0.2vdd to 0 . 8vdd 4 m h z ? 100 m hz 3.0 ns ckou t, 0.2vdd to 0 . 8vdd 100 m hz ? 150 m hz 2.5 ns output c lock fa ll t ime (4)(7) t fall cko u t, 0.2vdd to 0 . 8vdd 150 m hz ? 200 m hz 2.0 ns output clock jitter (4)(7) jit cko u t, period, 1 s 15 p s output lock time (6) t l ock cko u t, po w er - up 1 ms
a k8 1 42 jan- 09 ms093 2 - e - 01 - 6 - t he brand name of a kemd ? s ic ? s serial interface i2c sla v e mode a c ch a racteristics all specificat ions at vdd1: 3.3v, vdd2/vdd3: 1.8 v , ta: - 3 0 to +85 , unless otherw ise not ed (*) design valu e. s c l ( i n) s d a ( i n) s da ( o u t) tf tr tsu.s ta thd.s ta tsu.s to tsu.dat thd.dat taa tdh tbuf tlow thigh parameter s y mbol conditions min max unit scl clock frequency fscl 400 khz scl clock lo w period tl ow 4.7 us scl clock hig h period thigh 4.0 us pulse w idth of spikes w hich must be suppressed ti 100 ns slc lo w to sda data out taa 0.1 3.5 us bus free time bet w een a stop and start condit ion tbuf 4.7 us start condition hold time thd.sta 4.0 us start condition se t up time (for a repea t ed sta r t c ondition) tsu.sta 4.7 ms data in hold time thd.dat 0 us data in setup time tsu.dat 200 ns sda and scl rise time tr (*) 1.0 us sda and scl fall time tf (* ] 0.3 us stop condition setup time tsu.sto 4.0 us data out hold time tdh 100 ns
a k8 1 42 ms0932 - e - 01 jan- 09 - 7 - t he brand name of a kemd ? s ic ? s function description i2c interf ace read/ w rite perf orm ance of i2c interf ace is expr essed belo w . t he de vice ad dress #1 of ak81 42 is f ixed as ? 1010 ? . t he d evice a ddr ess #2 is set b y a0 , a1 p in s. device address of AK8142 by te w tire ope ration by t e w rite o perat ion is d escribed be lo w . data m ust be sent af ter send ing 8 b its ad dress and rece ivin g ac k. byte w rite 1 0 1 0 d ev i ce ad d r e ss d ev i ce a d dr e ss 0 r w addr e ss ( m sb fir s t) d a ta (msb f i r s t) s t a r t sda -1 -2 / a c k a c k a c k s t o p page w rite op e ration pa g e w ri t e o pera t ion is de s cribed b el o w . o n l y l o wer 4 bits of a d dress are valid. u pper 4 bits are f ixed as ? 1111 ? . t heref ore the ad dress w h ich is w ritte n af ter ? 1 111 1111 ? becom es ? 1111 0000 ? . page w rite dev ice addre ss d ev i ce addr e ss r w addr e ss ( m sb fir s t) d a ta ( addr e ss ) s t a r t s da -1 -2 / a c k a c k a c k d a ta a c k ( addr e ss +1 ) 1 0 1 0 0 a c k s t o p d a ta a c k ( addr e ss +n ) ? ? ?? curren t ad d re s s read current a ddress read op eratio n is described be lo w . t he d ata t hat is read b y th is operat ion is o bta ine d as ? last accessed ad dress + 1 ? . t heref ore, it is conseq uen t to ret urn ? 00 00 0 000 ? af ter accessing th e a ddress ? 0000 1111 ? . current addres s r ead 1 0 1 0 d ev i ce addr e ss d ev i ce addr e ss 1 r w d a ta ( m sb f irst) s t a r t s da -1 -2 / a c k n o a s t o p c k 1 0 1 0 1 a1 a0 r/w device a dress#2 device a dress#1
a k8 1 42 jan- 09 ms093 2 - e - 01 - 8 - t he brand name of a kemd ? s ic ? s random r e ad rand om read operat ion is described be lo w . it is nece ssary t o o perat e ? dum m y write ? bef ore sen ding re ad co m m and. dum m y w r ite is to send the ad dress to read. ran d o m read 1 0 1 0 d ev i ce addr e ss d e v ice addr e ss 0 r w addr e ss ( m sb f i rst) s t a r t s da -1 -2 / a c k a c k s t a r t 1 0 1 0 d ev i ce addr e ss -1 n o a s t o p c k du mm y w r i te d e v ice addr e ss 1 r w -2 / a c k d a ta ( m sb fi rst) sequent ia l r e ad se q uen t ia l re a d o perat ion is described belo w . i t is p ossible to re ad n ext ad dress seque ntially b y send in g ack inst ead of stop cond it ion. seq uent ia l read sda d ev i ce addr e ss 1 r w -2 / a c k d a ta ( m sb f ir s t) ( addr e ss ) n o a s t o p c k a c k d a t a ( m sb f ir s t) (addr e ss+1 ) a c k ???? a c k d a t a (msb f i rst) (addr e s s+ n ) ???? change data cha n ge d ata oper a tio n is d escribed b elo w . it is a v a ila b le when scl is lo w. chan ge d ata s da s cl d a t a s t a ble d a ta ch a n ge start / stop timing start / s t op t i m ing is d escribed bel o w . t he se q uence is started w h en sda g o es f ro m high to lo w during scl is high. t he se que nce is stopp ed when sd a g oe s f ro m low to high durin g scl is h ig h. start / st op t im ing s da s cl s t a rt s t op
a k8 1 42 ms0932 - e - 01 jan- 09 - 9 - t he brand name of a kemd ? s ic ? s register m ap fa ? ff has 2 dimensions w hich ar e selectable by bank bit. zer o is ret urned w hen ? ? ? bits are read. bottom part: reset value *not e t he po wer - on - reset d oes not rese t ? sft rst ? of register f7. address d7 d6 d5 d4 d3 d2 d1 d0 note ? ? ? ? ? ? frac[17] frac[16] ff 0 0 si g ma - delt a fraction frac[15] frac[14] frac[13] frac[12] frac[11] frac[10] frac[9] frac[8] fe 0 0 0 0 0 0 0 0 frac[7] frac[6] frac[5] f rac[4] frac[3] frac[2] frac[1] frac[0] fd 0 0 0 0 0 0 0 0 ? int[6] int[5] int[4] int[3] int[2] int[1] int[0] fc 0 1 0 0 0 0 0 si g ma - delta integer ? outc[2] outc[1] outc[0] odiv p g[3] odiv p g[2] odiv p g[1] odiv p g[0] fb 1 1 1 0 1 1 1 outdiv mdivc [3] mdivc[2] mdivc[1] mdivc[0] mdivp[ 3] mdivp[ 2] mdivp[ 1] mdivp[ 0] fa 0 1 1 0 0 0 0 1 mdiv ? ? ? ? rsrv rsrv rsrv rsrv f9 0 1 0 1 reserve ? ? ? ? rsrv rsrv rsrv rsrv f8 0 0 0 0 reserve bank ban k wr ctlfsel ckof f [1] ckof f [0] rsrv pd sftrs t f7 0 0 0 0 0 0 0 0 reset bank ? ? ? ? ckouten[1] refoten[0] refoten[1] refoten[0] f6 0 0 0 0 outbuf ? ? ? ? ? ? dumon dither f5 0 1 si g ma - delta f4 ? ? ? ? ? ? ? ? test ? ? ? ? ? ? ? ? test f1 ? ? ? ? ? ? ? ? test r egisters f1 t o f4 are f or test pur p ose o nl y . d o no t a ccess these registers.
a k8 1 42 jan- 09 ms093 2 - e - 01 - 10 - t he brand name of a kemd ? s ic ? s register definitions ref er ? frequenc y s etting procedure ? o n p age 15 f or de tails. address ff, f e, fd address d7 d6 d5 d4 d3 d2 d1 d0 frac[17] frac[16] frac[15] frac[14] frac[13] frac[12] frac[11] frac[10] frac[9] frac[8] frac[7] frac[6] frac[5] frac[4] frac[3] frac[2] frac[1] frac[0] frac[ 1 7:0] frac t ional n f racti o nal part set t ings frac[17:0] a value decimal f r ac t ion 01 111 1 111 1 111 1 1111 +131071 0.49999619.. 01 111 1 111 1 111 1 11 10 +131070 01 0000 0000 0000 0000 +65536 0.25 00 0000 0000 0000 0001 +1 0.00000381.. 00 0000 0000 0000 0000 0 0 1 1 111 1 111 1 111 1 1111 - 1 - 0.00000381.. 1 1 111 1 111 1 111 1 11 10 - 2 1 1 0000 0000 0000 0000 - 65536 - 0.25 10 0000 0000 0000 0001 - 131071 - 0.49999619.. 10 0000 0000 0000 0000 - 131072 - 0.5 fraction a l p art o f n is e x pressed b y a /2 18 . h ere, th e nu m erator a is de f in e d b y f r ac b its. f r ac is treated as 2 ? s c o m ple me nt which is a b le to s e t f r o m - 2 17 up t o +2 17 . c onse q u e nt ly , it is possible to s et f r o m - 0.5 to +0 . 5 f or f ractional part o f n. f r a c [ 17:0] settings a re updated after w riting register ff. setting pro c edure should be 1.fd, 2. f e and then 3.ff. address fc addr ess d7 d6 d5 d4 d3 d2 d1 d0 fc int[6] int[5] int[4] int[3] int[2] int[1] int[0] in t [5:0] frac t ional n in t egr a l p a rt setti n gs int[6:0] integr al value 000 0000 - 001 1000 prohibited 001 1001 25 001 1010 26 1 10 00 11 99 1 10 0100 100 1 10 0101 - 11 1 1111 prohibited *n o te d o no t set an y v a l ue except ? 25 ? - ? 1 00 ? .
a k8 1 42 ms0932 - e - 01 jan- 09 - 11 - t he brand name of a kemd ? s ic ? s address fb address d7 d6 d5 d4 d3 d2 d1 d0 fb outc[2] outc[1] outc[0] odivpg[3] odivpg[2] odivpg[1] odivpg[0] ou t c[2] p rogram m able divider inp ut select 0 vco output ( not divided) 1 vco 1/2 ou t put ou t c[1:0] pll ou t put s e lect outc[1:0] 0 0 vco output ( not divided) 0 1 vco 1/2 ou t put 1 0 vco 1/4 ou t put 1 1 vco programmable divide r output odivpg [ 3:0] progra m m able divider c o ntrol odivpg[3:0] dividing value 0 0 0 0 ( fi x ed output) 0 0 0 1 4 0 0 1 0 6 0 0 1 1 8 0 1 0 0 10 0 1 0 1 12 0 1 1 0 14 0 1 1 1 16 1 0 0 0 18 1 0 0 1 20 1 0 1 0 22 1 0 1 1 24 1 1 0 0 26 1 1 0 1 28 1 1 1 0 30 1 1 1 1 ( fi x ed output) 1/4 1/2 1/2 progra m m able div. s e l pllo ut odiv outc[1:0] odivpg[3:0] out c[2] vco s e l
a k8 1 42 jan- 09 ms093 2 - e - 01 - 12 - t he brand name of a kemd ? s ic ? s address fa address d7 d6 d5 d4 d3 d2 d1 d0 fa mdivc[3] mdivc[2] mdivc[1] md ivc[0] mdivp[3] mdivp[2] mdivp[1] mdivp[0] mdivc[3] program m able divider inp ut select 0 clkin 1 clkin 1/2 mdivc[2] 3or4 d ivi d er select 0 3 divider 1 4 divider mdivc[1 : 0] m divider dividing v a lue s e tti n gs mdivc[1:0] dividing value 0 0 1 0 1 2 1 0 3or4 1 1 programmable mdivp[ 3 :0] progra m m able divider c o ntrol mdivp[3:0] dividing value 0 0 0 0 prohibited 0 0 0 1 2 0 0 1 0 3 0 0 1 1 4 0 1 0 0 5 0 1 0 1 6 0 1 1 0 7 0 1 1 1 8 1 0 0 0 9 1 0 0 1 10 1 0 1 0 11 1 0 1 1 12 1 1 0 0 13 1 1 0 1 14 1 1 1 0 15 1 1 1 1 prohibited 1/3 or 1/4 1/2 1/2 progra m m able div. s e l mdiv mdivc[1 :0] mdivp[3:0] mdivc[3] s e l phase compa r ator cloc k in mdivc[2]
a k8 1 42 ms0932 - e - 01 jan- 09 - 13 - t he brand name of a kemd ? s ic ? s address f9, f8 address d7 d6 d5 d4 d3 d2 d1 d0 f9 reserved reserved reserved reserved f8 reserved reserved reserved reserved these regis t ers are reserved . set 05he x and 00he x to f9 and f8, r espec t ively. address f7 address d7 d6 d5 d4 d3 d2 d1 d0 f7 bank ban k wr ctlfsel ckoff[1] ckoff [0] reserved pd sftr st ba nk access register select f or f reque nc y set tin gs 0 bank0 v alid w hen ctlfsel= ? 0 ? 1 bank1 v alid w hen ctlfsel= ? 0 ? ba n k wr select t h e ba n k t o w rite 0 bank0 1 bank1 c t lfsel select f uncti o n f or the f sel pin 0 invalid se t invalid w hen register is se t. 1 v alid frequency selection bank is selec t able w ith fse l pin. ckoff[1] contr o l r efou t output b u f f er 0 output enable 1 output disenable (500k - ohm p ull do wn ) ckoff[0] contr o l pll out p ut b u ff er 0 output enable 1 output d isenable (500k - ohm p ull do wn ) reserved this bit is r eserved. se t to ? 0 ? . pd po w er do wn control 0 pow er up 1 po w er do w n (pl l analog p art) output tu r ns to ? h ? . sf t rst so f tware reset c o ntr ol 0 reset cancel 1 reset ( p l l digi t al p art and regis t er) se t t o ? 0 ? t o cancel th e so f tware reset.
a k8 1 42 jan- 09 ms093 2 - e - 01 - 14 - t he brand name of a kemd ? s ic ? s address f6 address d7 d6 d5 d4 d3 d2 d1 d0 f6 D D D D cko u ten[1] cko u ten[0] refout e n[1] refout e n[0] ckou t en[1: 0] contr o l c kou t bu ff er drivabili ty cko u ten[1:0] 0 0 high ( x 3) 0 1 m iddle ( x 2) 1 0 m iddle ( x 2) 1 1 lo w ( x 1) refou t en[1: 0] contr o l r efou t bu ff er dr i va b ili ty refout e n[1:0] 0 0 high ( x 3) 0 1 m iddle ( x 2) 1 0 m iddle ( x 2) 1 1 lo w ( x 1) address f5 address d7 d6 d5 d4 d3 d2 d1 d0 f5 D D D D D D d u m on dither dumon contr o l sdm (sigm a delt a mo du lat or) du m on 0 normal mode 1 bypassing sdm set this w hen using pl l w ith integer only. di t her fraction a l n divider set t in gs dither 0 perform as frac t ional part is 0. set this w hen using pll w ith integer only. 1 normal mode address f4 ? f1 t hese registers are t est pr o pose o n l y . d o n o t access these a ddress.
a k8 1 42 ms0932 - e - 01 jan- 09 - 15 - t he brand name of a kemd ? s ic ? s frequen c y setting procedure output f requ enc y of ckout is determ ined b y refcl k dividing va lue (mdiv ) , o ut put divid ing va lu e (odi v), fractiona l n dividin g value (int ,frac ) . t hese param et er s should be set as d escribed belo w. step1. d eciding vco bas e frequenc y. t his f requenc y (f vco) is dec ide d f ro m output f requenc y and o utpu t d ivid ing va lu e (address fb). note: set vco f requ enc y b et w ee n 1 00mh z t o 2 00mh z. set odi v bit to ? 1 ? when ou tput f req ue nc y exceeds 10 0mh z. step2. d eciding pha se co mparison frequenc y. set m d ivid er as th is f reque nc y b ecom es betw e en 2mh z t o 4mh z. step3. d eciding f eedbac k div iding v alue. t his valu e is decid ed b y vco f requenc y (f vco) an d phase com parison f requenc y (f cm p). 7 bits int egra l part an d 18 b its f ractiona l part (signe d 2 ? s co m plem ent) is necessary to be se t. integra l p art (int ) = rou nd ( f vco / f cm p ) fractiona l p art (frac) = rou nd ( ( f vco / f cm p ) ? int ) x 2 18 ) e x sample1) input 27m hz, output 123.75m hz 1. vco frequency: 123.75m hz odiv = 1 2. phase compar ison fr equency: 3m hz mdiv = 9 27m h z / 9 = 3m hz 3. feedback dividing value: 41.25 int = 41d, frac = 65536d int = round ( 123. 75 / 3 ) = r ound ( 41.25 ) = 41d frac = round ( ( 41.25 ? 41 ) x 2 18 ) = 65536d output frequency error : 0ppm regist er settings of ex sample1) [address] [value] [ contents ] 0 f7 0 08 clear sftrst, bank0, fsel=invalid, refout=off 0x fa 0x 38 mdiv 9 0x fb 0x 00 odiv 1 0x fc 0x 29 int 41 0x fd 0x 00 frac (low er 8bits) 0x fe 0x 00 frac( m edium 8bit s) 0x ff 0x 01 frac(upper 2bits) frac=655536d e x sample2) input 16m hz, output 24.576m hz 1. vco frequency: 147.456m hz odiv = 6 2. phase compar ison fr equency: 4m hz mdiv = 4 16m h z / 4 = 4m hz 3. feedback divi ding value: 36.864 int = 37d, frac = - 35652d int = round ( 147. 456 / 4 ) = r ound ( 36. 864 ) = 37d frac = round ( 36.864 ? 37 ) x 2 18 ) = - 35652d output frequency error : 0.043ppm ( 1.0 6 hz ) regist er settings of ex ample2) [address] [valu e] [ contents ] 0 f7 0 08 clear sftrst, bank0, fsel=invalid, refout=off 0x fa 0x 06 mdiv 4 0x fb 0x 32 odiv 6 0x fc 0x 25 int 37 0x fd 0x bc frac(low er 8bits) 0x fe 0x 74 frac( m edium 8bit s) 0x ff 0x 03 frac(upper 2bits) frac= - 3565 2d
a k8 1 42 jan- 09 ms093 2 - e - 01 - 16 - t he brand name of a kemd ? s ic ? s v dd 1 / 2 /3 po w er - on - r e s et i n t e rn a l v r ef r eset i 2 c i n t e r f ac e i np u t a va i l a b le m i n : 5 0 0us s c l / s da v dd *0 .9 m a x : 1 ms p o w er up sequence sup pl y ing pr oper vo ltag e to the po w er pins. * note : vdd1, vdd 2, vdd3 m ust be supplied sim ultan eousl y. po w er - on - reset is execu ted b y se tting r eset = ? l ? d uring st art up. scl / sd a ar e accept able 1m s later. *note : w hen using r eset sig na l, it tak es 500us af ter releasing t he r eset to ac cept sc l / sd a access. reset circuit to reset this ic, these tree methods are available. 1) inter nal pow er - on - reset 2) hardw are reset by reset pin 3) softw are reset by ? sftsrt ? of r egist er f7 the ? sftrst ? bit is not cleared by pow er - on - reset. it should be manually set to ? 0 ? af ter pow er- on - reset if it is necessary . reset pin r vref sftr st p w ron rst regis t er reset e x cept sftrst bit sft rst bit
a k8 1 42 ms0932 - e - 01 jan- 09 - 17 - t he brand name of a kemd ? s ic ? s package information mechanical data (units :mm) marking a: #1 pin in dex b: product fam ily log o *) c: part num ber c: date code (5digits) *) a km is the bran d n am e of akemd ? s ic ? s. a km an d th e logo - - are the bran d of akemd ? s ic ? s and id ent if y that akemd co ntinues t o off er the best cho ice f or hig h perf orm ance m ixed - signal so lut io n un der th is bran d. rohs compliance all integr ated circuits f orm asa hi kasei emd corpor ation (akemd) assem bled in ?lead - f ree? pack ages* are f ull y com plia nt with r oh s. (*) rohs compliant product s fr om akem d are identified w ith ?pb free? lett er indication on product label posted on the anti - shield bag and box es.
a k8 1 42 jan- 09 ms093 2 - e - 01 - 18 - t he brand name of a kemd ? s ic ? s important notice t hese products and th e ir speci f icati o ns are subject to change wit h out n otic e . be f ore consideri n g a n y use or applica t ion, cons u l t the asa h i kas e i m icro s y s t e m s co., l t d. (akm) sa l e s of f ice or authoriz ed distri b utor concer n i n g t h eir current status. akm assum es no liab ilit y f or inf ringem ent of an y p atent , inte llect ual prop ert y , or oth er rig ht in t he app licat ion or use of an y inf orm ation conta ine d h erein. a n y export o f these pro d ucts , or devices or s y ste m s cont a i n ing t h e m , m a y requ ire an export license or other off icial ap proval u nde r the la w an d regu lat ions of the countr y of export perta ining to custom s and tariff s, currenc y exchan ge, or strateg ic m aterials. akm prod ucts are ne ither inte nde d nor a uthor ized f or use as critical com po n ents in an y s af et y , life support, or oth er ha zar d re late d d evice or s y st em , and akm assum es no responsibilit y re lat in g to an y such use, except with t he express w rit ten co nsent of the re present ative direct or of akm. as used here: (a) a ha zard relate d d evice or s y st em is one d esign ed or inte nde d f or lif e su pport or m aintenance of saf et y or f or application in m edicine, aerospace , nuclear energ y , or oth er f ields, in w h ich its f ailure to f unction or p erf orm m a y r eas ona bl y b e expect ed to result in loss of lif e or in signif ican t injur y or dam age to p erson or pr ope rt y. (b) a critica l com ponen t is one whose f ailure to f unct ion o r perf orm m a y re asona bl y be exp ected to result, whet her direct ly or indirect ly , in t he loss of t he saf et y or eff ectiven ess of t he d evice or s y stem containing it, a nd which m ust theref ore m eet ver y h igh standards of perf orm ance and relia bilit y. it is the respons ibilit y of the bu y er or distribut or of an akm pro duct w ho d istribut es, disposes of , or otherw ise places the produ ct with a t hird part y to n ot if y th at part y in ad va nce of the ab ove cont ent and condit io ns, an d t he bu y er o r distrib utor agrees to assum e an y an d a ll respo nsib ilit y and liab ilit y f or and hold akm harm less f ro m a n y a nd a ll cla im s arising f ro m the use of said product in the absence of such notif icat ion.

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